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RT9241A/B
Two-Phase DC/DC Controller for CPU Core Power Supply
General Description
The RT9241A/B is a two-phase buck DC/DC controller integrated with all control functions for high performance processor VRM. The RT9241A/B drives 2 buck switching stages operating in 180 degree phase shift. The twophase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9241A/B regulates both easily set voltage and current loops. Precise current sharing for power stage is achieved by differential input current sense and processing circuit. The settings of current sense, droop tuning and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The RT9241A/B uses a 5-bit DAC of 1.1V to 1.85V (25mV/step) output with load current droop compensation to meet the strict VRM transient requirement. The IC monitors the VCORE voltage for PGOOD and over voltage protection. Soft start, over current protection and programmable under voltage lockout are also provided to assure the safety of microprocessor and power system.
Features
Two-Phase Power Conversion VRM 9.0 DAC Output with Active Droop Compensation for Fast Load Transient Precise Channel Current Sharing with Differential Sense Input Hiccup Mode Over Current Protection Programmable Under Voltage Lockout and Soft Start High Ripple Frequency, (Channel Frequency Times Channel Number) 100kHz Version (RT9241B) for Lower Switching Loss RoHS Compliant and 100% Lead (Pb)-Free
Applications
Power Supply for Server and Workstation Power Supply for High Current Microprocessor
Pin Configurations
(TOP VIEW)
VID4 VID3 VID2 VID1 VID0 COMP FB ADJ DVD SS 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PGOOD ISP1 PWM1 PWM2 ISP2 VSEN GND ISN1 ISN2
Ordering Information
RT9241A/B Package Type S : SOP-20 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Operating Frequency Version A : 200kHz B : 100kHz
SOP-20
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating. DS9241AB-05 March 2007 www.richtek.com 1
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RT9241A/B
+5V 12V 1uF 1uF 100uF/16V
Typical
1uH
12V 1uF 1
Q1 PHB83NO3LT
Typical Application Circuit
VID4 VID4 VDD PGOOD 1uF PHASE RT9600 0.01uF 5
Q2 PHB95NO3LT
1 7 PGOOD 8 2uH 2 VID3 VID2 VID1 VID0 COMP ISP1 FB ADJ GND
Typical
20 19
10K
+5V 3 4 PWM1 PWM LGATE GND 4 18 12 2.4K 1uF 2.4K 5 6 7 8 ISN1 13 14 VSEN 11 ISN2 1uF 16 3 2.4K 7 6 VCC PVCC 2 BOOT UGATE ISP2 15 2.4K 12V 17 3
VID3
6 VCC PVCC
2 BOOT UGATE
VID2
V CORE 1500uF 1500uF
2.4K
6.6nF 24K
VID1
VID0
33pF
1K
100uF
12V
9 DVD
1 8 5
1uF
Q3 PHB83NO3LT
2uH 0.01uF LGATE
Q4 PHB95NO3LT
13K 10 SS RT9241A PWM2
PHASE RT9600 PWM
1500uF
1500uF GND 4
2.4K
0.1uF
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+5V 10 1uF 1.2uH 12V 1uF 1000uF 12 x1500uF
PHB83N03LT
12V 11 BOOT1 VDD PVCC UGATE1 PHASE1 PWM1 RT9602 4
PHB95N03LT
14
1uF
VID4 VID4 VID3 2uH 13 VID2 VID1 VID0 ISP1 ISN1 12 3K 18 COMP FB ADJ VSEN 13 GND ISP2 15 3K 2uH
PHB83N03LT
1 VDD PGOOD 17 3K 0.01uF 19 PGOOD 2 3 4 PWM1 5 6 7 8 14 1000uF
20
10K 1uF
+5V
VID3
5
VID2
2.4K
6.6nF 24K
VID1
1
VID0
LGATE1 PWM2 9
2 3 UGATE2 GND 6
33pF
2.4K
1uF
8
PGND PHASE2 7 1uF 0.01uF BOOT2 10
13K 9 DVD RT9241A 10 SS ISN2 PWM2 16 11 3K
LGATE2
12V
x1500uF
2.4K
PHB95N03LT
0.1uF
RT9241A/B
V CORE
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Function Block Diagram
DVD
VDD PGOOD 120% VDAC VID0 VID1 VID2 VID3 VID4 DAC 108% VDAC 92% VDAC
Power On Reset
Oscillator
+ + + OVP, PGOOD POR Logic
INH
INH PWM Logic + & Driver PWMCP INH Current Balance Processor + PWMCP + + PWM Logic & Driver
PWM1
PWM2
Current Limit
VSEN CS1 ADJ Droop Control + EA CS2 SS Control
ISP1 ISN1 ISP2 ISN2
FB GND
COMP
SS
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Functional Pin Description
VID4, VID3, VID2, VID1 and VID0 ( Pin1,2,3,4,5) DAC voltage identification inputs for VRM9.0. These pins are TTL-compatible and internally pulled to VDD if left open. COMP (Pin 6) Output of the error amplifier and input of the PWM comparator. FB (Pin 7) Inverting input of the internal error amplifier. ADJ (Pin 8) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the amount of load droop. This pin should not be opened. DVD (Pin 9) Programmable power UVLO detection input. Trip threshold = 1.25V at VDVD rising SS (Pin 10) Connect this SS pin to GND with a capacitor to set the start time interval. Pull this pin below 1V (ramp valley of saw-tooth wave in pulse width modulator) to shutdown the converter output. ISN1 (Pin 12), ISN2 (Pin 11) Current sense inputs from the individual converter channel's sense component GND nodes. GND (Pin 13) Ground for the IC. VSEN (Pin 14) Power good and over voltage monitor input. Connect to the microprocessor-CORE voltage. ISP1 (Pin 18), ISP2 (Pin 15) Current sense inputs for individual converter channels. Tie this pin to the component sense node. PWM1 (Pin 17), PWM2 (Pin 16) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. PGOOD (Pin 19) Power good open-drain output. VDD (Pin 20) IC power supply. Connect this pin to a 5V supply.
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Table 1 Output Voltage Program
Pin Name VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal Output Voltage DACOUT Off 1.100V 1.125V 1.150V 1.175V 1.200V 1.225V 1.250V 1.275V 1.300V 1.325V 1.350V 1.375V 1.400V 1.425V 1.450V 1.475V 1.500V 1.525V 1.550V 1.575V 1.600V 1.625V 1.650V 1.675V 1.700V 1.725V 1.750V 1.775V 1.800V 1.825V 1.850V
Note: (1) 0:Connected to GND (2) 1:Open
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Absolute Maximum Ratings
Supply Voltage ---------------------------------------------------------------------------------------------------- 7V Input, Output or I/O Voltage ------------------------------------------------------------------------------------ GND-0.3V to VDD+0.3V Power Dissipation, PD @ TA = 25C SOP-20 ------------------------------------------------------------------------------------------------------------- 0.625W Package Thermal Resistance SOP-20, JA ----------------------------------------------------------------------------------------------------------------------------------------------------- 110C /W Ambient Temperature Range ----------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range ----------------------------------------------------------------------------------- 0C to 125C Storage Temperature Range ----------------------------------------------------------------------------------- -40C to 150C Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------- 260C
Electrical Characteristics
(VDD = 5V, GND = 0V, TA = 25C, unless otherwise specified)
Parameter VDD Supply Current Nominal Supply Current Power-On Reset VDD Rising Threshold VDD Falling Threshold Hysteresis VDVD Rising Trip Threshold Oscillator Frequency Ramp Amplitude Ramp Valley Maximum On Time of Each Channel Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID4) Input Low Voltage DAC (VID0-VID4) Input High Voltage DAC (VID0-VID4) Bias Current PWM Controller Error Amplifier DC Gain Bandwidth Slew Rate RT9241A RT9241B
Symbol
Test Conditions
Min
Typ
Max
Units
IDD
PWM 1,2 Open
--
4
10
mA
4.2 -0.2 1.19
4.35 3.85 0.6 1.25
4.6 --1.31
V V V V
For each phase
170 85 -1.0 70
200 100 1.7 1.3 75
230 115 --80
kHz V V %
-1.0 -2.0 20
---28
+1.0 0.8 -36
% V V A
--CL = 10pF --
85 10 5
----
dB MHz V/s
To be continued
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RT9241A/B
Parameter Current Sense GM Amplifier ISP 1,2 Full Scale Source Current ISP 1,2 Current for OCP Protection SS Current Over-Voltage Trip (VSEN/DACOUT) Power Good Upper Threshold (VSEN/DACOUT) Lower Threshold (VSEN/DACOUT) VSEN Rising VSEN Rising 106 86 110 90 114 94 % % VSS = 1V 8 118 13 122 18 126 A % 50 70 -75 --A A Symbol Test Conditions Min Typ Max Units
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Typical Operating Characteristics
Over Current Protection at PowerUp
PWM1 PWM2 PWM1 PWM2
Over Current Protection at Steady State
VSS
VSS
20A/Div
20A/Div
IOUT Time (25ms/Div)
IOUT Time (25ms/Div)
Current Sharing between Two Phases
PWM1 PWM2
Two-Phase Converter without Current Sharing
PWM1 PWM2
IL1
IL2
IL2 IL1 IL1 IL2 Time (5us/Div) IL1 IL2 Time (5us/Div)
The Hysteresis of VDD
1.6 1.4 1.2
1.6 1.4 1.2
The Hysteresis of VDVD
V CORE (V)
V CORE (V)
1 0.8 0.6 0.4 0.2 0 1 2 3 4 5 6
1 0.8 0.6 0.4 0.2 0 0.9 1 1.1 1.2 1.3 1.4 1.5
VDD (V)
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VDVD (V)
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RT9241A/B
Simplified Block Diagram Control Loops for a Two Phase Converter
+ PWMCP VDAC ADJ Droop Control Current Balance Processor + PWMCP
PWM Logic & Driver PWM Logic & Driver ISP1 ISN1
PWM1
PWM2
+ FB GND COMP + SS Control SS VIN CS2 EA CS1 -
ISP2 + ISN2 -
RT9600
RLOAD
COUT
VIN
RT9600 Voltage Loop
Current Loop
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RT9241A/B
Application Information
RT9241A/B is a two-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consists of RT9241A/B and its companion MOSFET driver provide high quality CPU power and all protection function to meet the requirement of modern VRM. Voltage control The reference of VCORE is provided by a 5-bit DAC of VRM9.0 specification. Control loop consists of error amplifier, two-phase pulse width modulator, driver and power components. Like conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal VC of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase saw-tooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current balance RT9241A/B senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals then produces the balancing signals injected to pulse width modulator. If the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. Load droop The sensed power channel current signals regulate the reference of DAC to form a output voltage droop proportional to the load current. The droop or so call "ctive voltage positioning" can reduce the output voltage ripple at load transient and the LC filter size. Fault detection The chip detects VCORE for over voltage and power good detection. The "hiccup mode" operation of over current protection is adopted to reduce the short circuit current. The in-rush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. MOSFET driver detection and converter start up RT9241A/B interface with companion MOSFET driver (like RT9600 or HIP660X series) for correct converter initialization. The tri-phase PWM output (high, low, high impedance) pins sense the interface voltage at IC POR acts (both VDD and VDVD trip). The channel is enabled if the pin voltage is 1.2V less than VDD. Please tie the both PWM output to driver input for correct converter startup. Current sensing setting RT9241A/B senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 1).
IX IBP IBN ISPX RSP RS ISNX R SN IL
Sample & Hold To Current Balance 2/3 IX To Droop Tune 2/3 IX To Over Current Detection 2/3 IX
GM +
Figure 1. Current Sense Circuit
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RT9241A/B
The sensing circuit gets I X = by local feedback. R SP RSP = RSN to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore,
IX(S/H) = IL(S/H) x RS RSP TOFF = ( VIN - VO VIN ) x TS , for switching IL(S/H) = IL(AVG) VO L
IL x R S
Protection and SS function For OVP, the RT9241A/B detects the VCORE by VSEN pin. Eliminate the parasitic delay and noise influence on the PCB path for fast and accurate detection. The trip point of OVP is 120% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VDD or VDVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 8% out of the normal level. The PGOOD open drain output pulls low when VOCRE exceeds the range. Soft start circuit generates a ramp voltage by charging external capacitor with 10uA current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the in-rush current and protect the power components. OCP is triggered if one channel S/H current signal IX> 75A. Controller forces PWM output latched at high impedance to turn off both high and low side MOSFET in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 10A current after it is less than 90% VDD. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4).
x
TOFF 2
period = TS
VIN - VO VO - ( ) x TS RS VIN IX(S/H) = IL(AVG) x 2L RSP
Falling Slope = Vo/L IL IL (AVG) Inductor Current IL (S/H)
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Figure 2. Inductor Current and PWM Signal Droop tuning The S/H current signals from power channels are injected to ADJ pin to create droop voltage. 2 VADJ = RADJ x IX 3 The DAC output voltage decreases by VADJ to form the VCORE load droop(see Figure 3).
VDAC COMP EA + FB + VADJ -
4V 2V 0V
COUNT = 1 COUNT = 2 VCORE OVERLOAD APPLIED IL
COUNT = 3 SS
0A
2/3 IX1
Ix
ADJ RADJ 2/3 IX2
T0T1
T2 TIME
T3T4
VDAC-VADJ
Figure 4
Figure 3. Droop Tune Circuit
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Two-Phase Converter and Components Function Grouping
12V VCC PVCC BOOT UGATE
+5V
VDD VID RT9241A/B
PHASE RT9600 PWM LGATE
GND
Compensation & Offset COMP FB VSEN ADJ Droop Setting
PWM1 ISP1 ISN1
12V VCC PVCC BOOT UGATE +VCORE
GND
PHASE RT9600 12V Driver Power UVLO DVD PWM2 PWM LGATE
GND SS ISP2 ISN2 Current Sense Components
Design Procedure Suggestion
Voltage loop setting a.Output filter pole and zero (Inductor, output capacitor value & ESR) b.Error amplifier compensation network Current loop setting a.Over current protection trip point setting by GM amplifier S/H current(current sense component Ron, ISPx & ISNx pin external resistor value, keep ISPx current = 75A at OCP condition) VRM load line setting a.Droop amplitude (ADJ pin resistor) b.No load offset (additional resistor in compensation network) Power sequence & SS DVD pin external resistor and SS pin capacitor PCB layout a.Kelvin sense for current sense GM amplifier input b.Refer to layout guide for other item
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RT9241A/B
Design Example for RT9241A
Two phase converter VCORE = 1.5V, VIN = 12V, full load current = 40Amp, droop voltage at full load = 120mV, OCP trip point for each power stage = 30Amp (at Sample/ Hold), low side MOSFET R DS(ON) = 6m at room temperature, L = 2H, C OUT = 9000F, capacitor ESR = 2m. 1.Compensation setting a. Modulator Gain, Pole and Zero Modulator Gain =
VIN VRAMP
Asymptotic Bode Plot of PWM Loop Gain
100 80 60 40
Uncompensated EA Gain
Gain (dB)
20 0 -20 -40 -60 10 10 100 100 1K 1000
Compensated EA Gain PWM Loop Gain Modulator Gain
10K 10000
100K 1M 10M 100000 1000000 10000000
saw-tooth wave amplitude VRAMP = 1.7V, modulator Gain = 8.6 = 18.7dB LC filter pole =
1
Frequency (Hz)
Figure 6. Asymptotic Bode Plot of PWM Loop Gain
1 2 LC = 1.2kHz
2.Over Current Protection setting OCP trip point current = 30A (at Sample/Hold),
IX = RDS(ON) x 30 A = 75A , RISP = 2.4K RSP
ESR zero = CRESR = 8.8kHz 2 b. EA compensation network Use type 2 compensation scheme (see Figure5) 1 1 FZ = FP = C1x C2 2 R2C1 2 R2( ) C1+ C2 mid-band gain =
R2 R1
Take the temperature rising for consideration, if MOSFET working temperature = 70C and the temperature coefficient = 5000ppm/C, RISP(70C) = RISP(27C) {RDS(ON)(70C)/RDS(ON)(27C)} = 1.75K 3.Droop setting Full load current of each power channel = 40A/2 = 20Amp, the ripple current = IL = 5 s x 1.5V 2 H x (11.5V 12V
I L 2 = 18.36A
x
. Choose R 1 = 2.4K,
R2 = 24K, C1 = 6.6nF, C2 = 33pF, get FZ = 1kHz, Fp = 200kHz, mid-band Gain = 10 = 20dB, modulator asymptotic Bode plot of EA compensation and PWM loop Gain Bode shown as Figure 6.
C1 C2 COMP EA + FB R2 C3 R3 R1 R3, C3 are used in type 3 compensation scheme (left NC in type 2) ROL DACOUT ROL for no load offset setting
) = 3.28A
, load current at S/H 20A VCORE
= IX(MAX) =
RDS(ON) x 18.36A RISP
, GM Amp S/H, RISP = RISN = 2.4K, IX(MAX) = 46A, required Droop = 120mV = 46Ax2x2/3xR ADJ, RADJ = 1.97K. Take the temperature rising for consideration, we just modify RISP like OCP setting.
Figure 5. EA Compensation Network
4.SS capacitor CSS = 0.1F is the suitable value for most application.
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Layout Guide
Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. 1.Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2 and ISN1,2, should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate stable current sensing. No Kelvin sense, no guarantee for stable operation! Switching ripple current path: a.Input capacitor to high side MOSFET b.Low side MOSFET to output capacitor c.The return path of input and output capacitor d.Separate the power and signal GND e.The switching nodes (the connection node of high/ low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f.Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 2.MOSFET driver should be close to MOSFET 4.The compensation, bypass and other function setting components should be near the IC and away from the noisy power path.
SW1
L1
VIN RIN
VOUT
COUT
V
CIN L2 SW2
RL
Figure.7 Power Stage Ripple Current Path
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RT9241A/B
Next to IC Pin(s) +12V +12V or +5V PVCC VCC CBP CBOOT Use Individual Metal Runs for Each Channel to help Isolate Output Stages LO1 PHASE CIN
Kelvin Sense
PWM
VCC CBP
+5VIN
ADJ COMP CC1
Next to IC Pin(s)
RT9600
VCORE
RT9241A/B
COUT RSIP RSIN Locate next to IC FB ISPx ISNx VSEN
CC2 RC Locate next to FB Pin
RFB
Parallel Trace Locate near Transistor
Figure.8 Layout Consideration
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Outline Dimension
A H M
J
B
F
C I D
Symbol A B C D F H I J M
Dimensions In Millimeters Min 12.598 7.391 2.362 0.330 1.194 0.229 0.102 10.008 0.381 Max 13.005 7.595 2.642 0.508 1.346 0.330 0.305 10.643 1.270
Dimensions In Inches Min 0.496 0.291 0.093 0.013 0.047 0.009 0.004 0.394 0.015 Max 0.512 0.299 0.104 0.020 0.053 0.013 0.012 0.419 0.050
20- Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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